A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation.
| Autor: | von Kaenel, Vincent, Aebischer, Daniel, Piguet, Christian, Dijkstra, Evert |
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| Zdroj: | Phase-Locking in High-Performance Systems; 2003, p383-390, 8p |
| Databáze: | Complementary Index |
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