Chapter 2: 0.5-μ 2M-Transistor BiPNMOS Channelless Gate Array.
| Autor: | Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Youichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe |
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| Zdroj: | High-Performance System Design; 1999, p112-116, 5p |
| Databáze: | Complementary Index |
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