Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication.
| Autor: | Kai-Shin Li, Ho, ChiaHua, Ming-Taou Lee, Min-Cheng Chen, Cho-Lun Hsu, Lu, J. M., Lin, C. H., Chen, C. C., Wu, B. W., Hou, Y. F., Lin, C. Yi., Chen, Y. J., Lai, T. Y., Li, M. Y., Yang, I., Wu, C. S., Fu-Liang Yang |
|---|---|
| Zdroj: | 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers; 2014, p1-2, 2p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|