A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.
| Autor: | Hashida, Takushi, Tomita, Yasumoto, Ogata, Yuki, Suzuki, Kosuke, Suzuki, Shigeto, Nakao, Takanori, Terao, Yuji, Honda, Satofumi, Sakabayashi, Sota, Nishiyama, Ryuichi, Konmoto, Akihiko, Ozeki, Yoshitomo, Adachi, Hiroyuki, Yamaguchi, Hisakatsu, Koyanagi, Yoichi, Tamura, Hirotaka |
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| Zdroj: | 2014 Symposium on VLSI Circuits Digest of Technical Papers; 2014, p1-2, 2p |
| Databáze: | Complementary Index |
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