Simulation of SSTL IO standard based power optimized parallel integrator design on FPGA.
| Autor: | Das, T, Pandey, B, Kumar, T, Kumar, Parkash, Kumar, Love |
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| Zdroj: | 2014 International Conference on Robotics & Emerging Allied Technologies in Engineering (iCREATE); 2014, p1-5, 5p |
| Databáze: | Complementary Index |
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