SRAM with c-axis aligned crystalline oxide semiconductor: Power leakage reduction technique for microprocessor caches.
| Autor: | Ishizu, Takahiko, Kato, Kiyoshi, Onuki, Tatsuya, Matsuzaki, Takanori, Tamura, Hikaru, Ohmaru, Takuro, Uesugi, Wataru, Isobe, Atsuo, Ohshima, Kazuaki, Tochibayashi, Katsuaki, Nei, Kosei, Noda, Kosei, Tsutsui, Naoaki, Atsumi, Tomoaki, Shionoiri, Yutaka, Goto, Gensuke, Koyama, Jun, Yamazaki, Shunpei, Goshima, Masahiro, Fujita, Masahiro |
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| Zdroj: | 2014 IEEE 6th International Memory Workshop (IMW); 2014, p1-4, 4p |
| Databáze: | Complementary Index |
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