FPGA-based implementation of M4RM for matrix multiplication over GF(2).
| Autor: | Kumar, Vivek, Kumar, Vinay B. Y., Patkar, Sachin B. |
|---|---|
| Zdroj: | 18th International Symposium on VLSI Design & Test; 2014, p1-2, 2p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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| Autor: | Kumar, Vivek, Kumar, Vinay B. Y., Patkar, Sachin B. |
|---|---|
| Zdroj: | 18th International Symposium on VLSI Design & Test; 2014, p1-2, 2p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|