| Autor: |
Shylashree, Nagaraja, Sridhar, Venugopalachar |
| Předmět: |
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| Zdroj: |
International Journal of Simulation: Systems, Science & Technology; 2013, Vol. 14 Issue 2, p35-41, 7p |
| Abstrakt: |
This paper presents a High speed, optimized multiplier architecture for a dual-field (DF) processor for elliptic curve cryptography (ECC). This processor can support the required operations in both galois prime field GF(p) and binary field GF(2m). The performance of the processor is enhanced by the judicious selection of proper type of coordinates in the arithmetic unit. The arithmetic unit is designed to provide dual-field multiplication and addition. The FPGA synthesis results show that the proposed dual-field ECC processor with Karatsuba method can reach a speed up to 124 MHz, consumes a power of 1091mW and occupies 3066 slices. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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