| Autor: |
Yan-Feng Lang, Ji-Zhong Shen, Liang Geng, Mao-Qun Yao |
| Předmět: |
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| Zdroj: |
Electronics Letters (Wiley-Blackwell); 7/17/2014, Vol. 50 Issue 15, p1052-1053, 2p, 4 Diagrams, 1 Chart |
| Abstrakt: |
A ternary clock generator (TCG) is proposed to settle its shortage. The TCG is implemented at the switch level with a simple structure of 24 MOS transistors and simulated at the layout level using the HSPICE software with TSMC 0.18 μm CMOS technology, showing that it works properly. The analyses show that the proposed TCG not only can output a ternary clock of high quality, meeting the clock's design requirements, but also can be fabricated with standard CMOS technology. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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