| Autor: |
Sumi, Yasuaki, Obote, Shigeki |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Consumer Electronics; Aug97, Vol. 43 Issue 3, p550, 9p, 7 Diagrams, 1 Chart, 5 Graphs |
| Abstrakt: |
Proposes two items for the fast frequency settling in the Phase Locked Loop (PLL) frequency synthesizer. Information on PLL frequency synthesizer; PLL frequency synthesizer utilizing the Frequency Detector Method Speedup Circuit (FDMSC); Short cut Lowpass Filter (LPF) method for the PLL frequency synthesizer utilizing the FDMSC. |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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