Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology.
| Autor: | Batra, Pooja, LaTulipe, Douglas, Skordas, Spyridon, Winstel, Kevin, Kothandaraman, Chandrasekharan, Himmel, Ben, Maier, Gary, He, Bishan, Gamage, Deepal Wehella, Golz, John, Lin, Wei, Vo, Tuan, Priyadarshini, Deepika, Hubbard, Alex, Cauffman, Kristian, Peethala, Brown, Barth, John, Kirihata, Toshiaki, Graves-Abe, Troy, Robson, Norman |
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| Zdroj: | 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S); 2013, p1-2, 2p |
| Databáze: | Complementary Index |
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