Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration.

Autor: Bhushan, Bharat, Yu, Minrui, Dukovic, John, Wong, Loke Yuen, Kitowski, Aksel, Park, Mun Kvu, Hua, John, Bolagond, Shwetha, Chan, Anthony C-T, Toh, Chin Hock, Sundarrajan, Arvind, Kumar, Niranjan, Ramaswami, Sesh
Zdroj: 2013 IEEE International Interconnect Technology Conference - IITC; 2013, p1-3, 3p
Abstrakt: We present fabrication, electrical characterization, and metrology analysis results of 5×50um TSVs for 3D integration. Specifically, electrical performance of blind TSVs is evaluated by capacitance-voltage (CV) and current-voltage (IV) measurements. Important electrical parameters such as oxide capacitance, minimum TSV capacitance, leakage current, and breakdown voltage are extracted and show good results. The capacitance values also closely match model predictions. The electrical testing data are further verified with a variety of materials analysis techniques. [ABSTRACT FROM PUBLISHER]
Databáze: Complementary Index