Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination.

Autor: Chew, Jason, Mahajan, Uday, Bajaj, Rajeev, Mirshad, Iad, Newcomb, Robert
Zdroj: 2013 IEEE International 3D Systems Integration Conference (3DIC); 2013, p1-6, 6p
Abstrakt: Through Silicon Vias (TSV) is a key technology for advanced 3DIC packaging, enabling improved device performance, integration of multiple functions in a single package and form factor reduction. TSV reveal CMP is one of the key processes in this integration scheme [1]. [ABSTRACT FROM PUBLISHER]
Databáze: Complementary Index