Trusted verification test bench development for Phase-Locked Loop (PLL) hardware insertion.
| Autor: | Kimura, Adam G., Liu, Kai-Wei, Prabhu, Siddharth, Bibyk, Steven B., Creech, Greg |
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| Zdroj: | 2013 IEEE 56th International Midwest Symposium on Circuits & Systems (MWSCAS); 2013, p1208-1211, 4p |
| Databáze: | Complementary Index |
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