Comparing layouts with HDL models: a formal verification technique.
| Autor: | Kam, T., Subrahmanyam, P.A. |
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| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; 1995, Vol. 14 Issue 4, p503-509, 7p |
| Databáze: | Complementary Index |
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