Modular architecture for high performance implementation of the FRR algorithm.
| Autor: | Sapiecha, K., Jarocki, R. |
|---|---|
| Zdroj: | IEEE Transactions on Computers; 1990, Vol. 39 Issue 12, p1464-1468, 5p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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| Autor: | Sapiecha, K., Jarocki, R. |
|---|---|
| Zdroj: | IEEE Transactions on Computers; 1990, Vol. 39 Issue 12, p1464-1468, 5p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|