| Autor: |
Yoshida, Toshio, Maruyama, Takumi, Akizuki, Yasunobu, Kan, Ryuji, Kiyota, Naohiro, Ikenishi, Kiyoshi, Itou, Shigeki, Watahiki, Tomoyuki, Okano, Hiroshi |
| Předmět: |
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| Zdroj: |
IEEE Micro; Nov2013, Vol. 33 Issue 6, p16-24, 9p |
| Abstrakt: |
Fujitsu's Sparc64 X is a processor for Unix servers that runs at a speed of 3 GHz and consists of 16 cores, a 24-Mbyte shared level-2 (L2) cache, memory controllers, I/O controllers, and system controllers for connecting multiple chips. The authors of this article enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer. The peak memory bandwidth is 102 Gbytes per second. These features realize extremely high-throughput performance. In addition, the authors added new functions to the processor core pipelines, which accelerate certain software tasks such as cryptographic processing. They call these functions "software on chip" (SWoC). Furthermore, they employ high-reliability technology used in mainframes to ensure stable operation of mission-critical systems. This article describes the past and current direction of the microarchitecture of the Sparc64 processor series, gives an overview of Sparc64 X, and presents results of testing the performance and power efficiency of SWoC. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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