Gate stack resistance and limits to CMOS logic performance.
| Autor: | Wachnik, R. A., Lee, S., Pan, L. H., Lu, N., Li, H., Bingert, R., Randall, M., Springer, S., Putnam, C. |
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| Zdroj: | 2013 Proceedings of the IEEE Custom Integrated Circuits Conference; 2013, p1-4, 4p |
| Databáze: | Complementary Index |
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