Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers.
| Autor: | Pieper, Leandro Zafalon, da Costa, Eduardo A. C., Monteiro, Jose C. |
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| Zdroj: | 2013 26th Symposium on Integrated Circuits & Systems Design (SBCCI); 2013, p1-6, 6p |
| Databáze: | Complementary Index |
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