On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM.
| Autor: | Schuster, S.E., Chappell, T.I., Chappell, B.A., Franch, R.L. |
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| Zdroj: | IEEE Journal of Solid-State Circuits; 1992, Vol. 27 Issue 7, p1073-1079, 7p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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