A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC.
| Autor: | Nogami, K., Sakurai, T., Sawada, K., Sakaue, K., Miyazawa, Y., Tanaka, S., Hiruta, Y., Katoh, K., Takayanagi, T., Shirotori, T., Itoh, Y., Uchida, M., Iizuka, T. |
|---|---|
| Zdroj: | IEEE Journal of Solid-State Circuits; 1990, Vol. 25 Issue 1, p100-108, 9p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|