A 4-Mbit DRAM with trench-transistor cell.
| Autor: | Shah, A.H., Wang, C., Womack, R.H., Gallia, J.D., Shichijo, H., Davis, H.E., Elahy, M., Banerjee, S.K., Pollack, G.P., Richardson, W.F., Bordelon, D.M., Malhi, S.D.S., Pilch, C.J., Tran, B., Chatterjee, P.K. |
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| Zdroj: | IEEE Journal of Solid-State Circuits; 1986, Vol. 21 Issue 5, p618-626, 9p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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