Iterated timing analysis with dynamic partitioning technique for bipolar transistor circuits.
| Autor: | Ishida, M., Nishigaki, M., Hayashi, K., Asai, H. |
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| Zdroj: | Proceedings of IEEE International Symposium on Circuits & Systems - ISCAS '94; 1994, Issue 1, p411-411, 1p |
| Databáze: | Complementary Index |
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