Verification of circuits described in VHDL through extraction of design intent.
| Autor: | Hoskote, Y.V., Moondanos, J., Abraham, J.A., Fussell, D.S. |
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| Zdroj: | Proceedings of 7th International Conference on VLSI Design; 1994, p417-420, 4p |
| Databáze: | Complementary Index |
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