Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 /spl mu/m CMOS process.
| Autor: | Amerasekera, A., McNeil, V., Rodder, M. |
|---|---|
| Zdroj: | International Electron Devices Meeting Technical Digest; 1996, p893-896, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|