A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation.
Autor: | Hayashi, F., Ohkubo, H., Takahashi, T., Horiba, S., Noda, K., Uchida, T., Shimizu, T., Sugawara, N., Kumashiro, S. |
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Zdroj: | International Electron Devices Meeting Technical Digest; 1996, p283-286, 4p |
Databáze: | Complementary Index |
Externí odkaz: |