A 0.5 /spl mu/m 3 V 1T1C 1 Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor.
| Autor: | Miyakawa, T., Tanaka, S., Itoh, Y., Takeuchi, Y., Ogiwara, R., Doumae, S.M., Takenakal, H., Kunishima, I., Shuto, S., Hidaka, O., Ohtsuki, S., Tanaka, S.-I. |
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| Zdroj: | 1999 IEEE International Solid-State Circuits Conference Digest of Technical Papers ISSCC First Edition (Cat No99CH36278); 1999, p104-105, 2p |
| Databáze: | Complementary Index |
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