A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM.
| Autor: | Chappell, T.I., Chappell, B.A., Schuster, S.E., Allan, J.W., Kepner, S.P., Joshi, R.V., French, R.L. |
|---|---|
| Zdroj: | 1991 IEEE International Solid-State Circuits Conference Digest of Technical Papers; 1991, p50-288, 239p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|