Architecture and performance models for scalable IP lookup engines on FPGA.
| Autor: | Yang, Yi-Hua E., Qu, Yun, Haria, Swapnil, Prasanna, Viktor K. |
|---|---|
| Zdroj: | 2013 IEEE 14th International Conference on High Performance Switching & Routing (HPSR); 2013, p156-163, 8p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|