Experiments and analysis to characterize logic state retention limitations in 28nm process node.
| Autor: | Dasnurkar, Sachin, Datta, Animesh, Abu-Rahma, Mohamed, Nguyen, Hieu, Villafana, Martin, Rasouli, Hadi, Tamjidi, Sean, Cai, Ming, Sengupta, Samit, Chidambaram, P R, Thirumala, Raghavan, Kulkarni, Nikhil, Seeram, Prasanna, Bhadri, Prasad, Patel, Prayag, Yoon, Sei Seung, Terzioglu, Esin |
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| Zdroj: | 2013 IEEE 31st VLSI Test Symposium (VTS); 2013, p1-6, 6p |
| Databáze: | Complementary Index |
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