A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
| Autor: | Yu, Kunzhi, Zheng, Xuqiang, Huang, Ke, Xuan, Ma, Wang, Ziqiang, Zhang, Chun, Wang, Zhihua |
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| Zdroj: | 2013 International Symposium onVLSI Design, Automation & Test (VLSI-DAT); 2013, p1-4, 4p |
| Databáze: | Complementary Index |
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