| Autor: |
Najam, Faraz, Yu, Yun Seop, Cho, Keun Hwi, Yeo, Kyoung Hwan, Kim, Dong-Won, Hwang, Jong Seung, Kim, Sansig, Hwang, Sung Woo |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Electron Devices; Aug2013, Vol. 60 Issue 8, p2457-2463, 7p |
| Abstrakt: |
Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current–voltage characteristics. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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