| Autor: |
Huang, Min, Mehalel, Moty, Arvapalli, Ramesh, He, Songnian |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Aug2013, Vol. 48 Issue 8, p1954-1962, 9p |
| Abstrakt: |
An energy efficient on-die 20-way set associative L3 cache of size 20 MB for the Intel® Xeon® processor E5 family is presented. It is manufactured in the Intel's 32-nm second generation of high-K dielectric metal gate process with 9-copper metal layers. The L3 cache design uses 0.2119 um^2 cell for the high density big array and 0.2725 um^2cell for the high performance smaller arrays. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs. The effective and rich redundancy design improves both yield and low voltage operations. The L3 cache achieves more than 20–40% energy efficiency when compared to previous generations and demonstrates wide operating ranges from 1.2 GHz at below 0.7 V to greater than 4.0 GHz at above 1.0 V. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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