| Autor: |
Srinivasan, J., Rajaram, S. |
| Zdroj: |
2013 International Conference on Information Communication & Embedded Systems (ICICES); 2013, p1057-1063, 7p |
| Abstrakt: |
This paper presents a low complexity hardware design for computing Singular Value Decomposition (SVD) of the radio communication channel characteristic matrix. The hardware developed is suitable for computing the SVD of a sequence of 3 ×3 complex-value matrices used in MIMO-OFDM standards, such as the IEEE 802.11n. The information of the right singular-vector matrix can be fed back to the transmitter for linear precoding to improve the error performance when facing the channel matrix with rank deficiency problem. The time for the SVD of one complex matrix is limited to about 400 ns. When the channels have short coherent time, the information derived by SVD should be sent from the receiver to the transmitter as soon as possible to keep the precoding performance. The algorithms to decompose the channel matrix were implemented using the Virtex-II xq2v1000-4bg575 FPGA from Xilinx as the target device with Maximum combinational path delay: 109.338ns. The implementation concentrates on utilizing the features of the FPGA to speed up operations and reduce the area required. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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