| Autor: |
Matthias, Thorsten, Huysmans, Frank, Burggraf, Juergen, Burgstaller, Daniel, Lindner, Paul |
| Zdroj: |
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC); 2012, p236-239, 4p |
| Abstrakt: |
3D stacked ICs (3Ds-IC) have been a hot topic for several years, but recent announcements from leading image sensor and memory manufacturers show that 3Ds-ICs finally move into high volume manufacturing. The main difference between a standard 2D wafer fab and a 3Ds-IC wafer fab is the ability to process both sides of an ultra-thin wafer and to manufacture through silicon vias (TSVs). Wide I/O DRAM is currently targeting 20μm thin wafers. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. However, the cost and cycle time of the main TSV manufacturing process steps etching, barrier/seed layer deposition and plating increases significantly with higher aspect ratio. Thinner wafers enable smaller TSV diameters and lower TSV aspect ratios and thereby enable lower cost for TSV manufacturing [1]. The implementation of thin wafer processing in high volume memory manufacturing has brought a significant change of the requirements. In the past the early adopters of thin wafer processing in the fields of power electronics and compound semiconductors designed the backside process flow around the ability to handle and process a thin wafer. Today stacked memory applications the compatibility with standard processes at highest yield is a must. The thin wafers today usually have microbumps on both sides. To ensure high yield for thermo-compression microbump bonding the thin wafers have to fulfil wafer fab cleanliness requirements after debonding. In a nutshell the industry demands standardized processes for thin wafer handling. The revolutionary ZoneBOND® technology achieves just that — standardized and material independent processes and equipment. Temporary bonding to a rigid support carrier and debonding after backside processing have been used for thin wafer handling/processing for many years. However, so far all the debonding methods imposed severe limitations on the manufacturability. For light induced debonding the carrier had to be transparent and for solvent based debonding the carrier had to be perforated. For thermally induced debonding, “slide-off debonding” the debonding temperature had to be below the reflow temperature of the solder bumps, which limited the maximal process temperature of the adhesive. In the past the debonding method, the adhesive properties and the carrier properties were closely linked to each other. This link between debonding method, adhesive and carrier imposed severe limitations on the manufacturability. With ZoneBOND® technology the debonding process is not at all a function of the adhesive any more — debonding has become a function of the carrier. Figure 1 shows the principle of the ZoneBOND® carrier. The ZoneBOND® carrier has two zones, which differentiate by the degree of adhesion between the adhesive and the carrier. The adhesion in the center zone is reduced, whereas full adhesion is at work in the edge zone. It is important to note that the surface of the device wafer does not have to be treated at all for ZoneBOND®, which makes the technology compatible with any kind of surface passivation. This is especially important with regards to assembly after thin wafer processing. Debonding methods which rely on surface modifications of the device wafer have the inherent risk of causing adhesion problems with the underfill material during die bonding. The debonding method is compatible with bumps or pillars in the bond interface as ... [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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