| Autor: |
Mittl, Steve, Swift, Ann, Wu, Ernest, Ioannou, Dimitris, Chen, Fen, Massey, Greg, Rahim, Nilufa, Hauser, Mike, Hyde, Paul, Lukaitis, Joe, Rauch, Stew, Saroop, Sudesh, Wang, Yanfeng |
| Zdroj: |
2012 IEEE International Reliability Physics Symposium (IRPS); 1/ 1/2012, p6-6A.5.7, 0p |
| Abstrakt: |
The reliability characterization of a high performance 32nm SOI CMOS technology featuring gate first High-K Metal Gate and embedded High-K Metal Fill DRAM is presented. This technology features high performance 0.9V thin dielectric devices and 1.5V thick dielectric I/O devices. Included are results of Hot Carrier, Bias Temperature, Planar and Trench Node TDDB, Gate to Contact, silicon eFUSE, SER, SRAM and Logic circuit reliability evaluations. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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