| Autor: |
Lim, Teck Siang, Cheong, CH, Tan, SH |
| Zdroj: |
2012 13th International Conference on Electronic Packaging Technology & High Density Packaging; 1/ 1/2012, p472-476, 5p |
| Abstrakt: |
Due to rapid growth of the microelectronics industry, the packaged device with smaller, low cost and high power performance becomes a high demand in the market nowadays. To fulfill the market development rate, flip chip interconnection is the most promising packaging solution. In this environment, the National Semiconductor Sdn. Bhd. (a subsidiary of Texas Instruments) performed a qualification run on Thin Shrink Small Outline Package (TSSOP) with Flip Chip on lead frame (FCOL) exposed die back (eDIE) technology. It has been reported that the most detrimental effect on reliability come from solder extrusion and mold adhesion. The solder extrusion observed like a thin sliver “flake” that partially adhered on the polyimide (PI) layer surface. The solder extrusion can be observed from Scanning Acoustical Microscopy (CSAM) image and SEM cross section image which shows as the delamination. The PI layer with isolation, “Island” is designed as a barrier in between two bumps to prevent solder extruded that connect together. To have better barrier effect by optimizing the PI layer thickness and the width size were further evaluated. Preconditioning was performed to screen out the samples with solder extrusion by doing the electrical testing (ATE). The thermal cycling test was proceeded to assess the reliability up to 500 cycles. The results indicated that the samples with the PI isolation passed the ATE without solder extrusion and no solder joint reliability issue observed. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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