| Autor: |
Yi-Hsun Chen, Chi-Heng Yang, Chang, Hsie-Chia |
| Zdroj: |
Proceedings of Technical Program of 2012 VLSI Design, Automation & Test; 1/ 1/2012, p1-4, 4p |
| Abstrakt: |
This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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