| Autor: |
Mendon, Ashwin A., Sass, Ron, Baker, Zachary K., Tripp, Justin L. |
| Zdroj: |
IEEE/IFIP International Conference on Dependable Systems & Networks Workshops (DSN 2012); 1/ 1/2012, p1-6, 6p |
| Abstrakt: |
A fast hardware-based checkpoint-restart mechanism is proposed in this paper. A circuit was developed and implemented on an FPGA as a proof-of-concept. Further the size and performance of this circuit was analyzed by instrumenting the cores and taking measurements with a commercial solid state (SATA2) drive. The same tests were measured using a modern Linux server with a conventional PCIe SATA2 host bus adaptor. The results suggest that the circuit would be a tiny fraction of a modern CMOS chip (less than 2%) while providing a significant performance advantage over a software-only solution. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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