| Autor: |
Zid, Mounir, Tourki, Rached, Scandurra, Alberto, Pistritto, Carlo |
| Zdroj: |
ICM 2011 Proceeding; 1/ 1/2011, p1-5, 5p |
| Abstrakt: |
In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for low-power and low-noise on-chip devices. The device is constructed around a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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