| Autor: |
Bachrach, Jonathan, Vo, Huy, Richards, Brian, Lee, Yunsup, Waterman, Andrew, Avizienis, Rimas, Wawrzynek, John, Asanovic, Krste |
| Zdroj: |
DAC Design Automation Conference 2012; 1/ 1/2012, p1212-1221, 10p |
| Abstrakt: |
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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