| Autor: |
Feilen, Michael, Ihmig, Matthias, Schwarzbauer, Christian, Stechele, Walter |
| Zdroj: |
22nd International Conference on Field Programmable Logic & Applications (FPL); 1/ 1/2012, p75-82, 8p |
| Abstrakt: |
Demodulation and decoding of second generation terrestrial digital video broadcasting (DVB-T2) signals on general purpose processor platforms is challenging in terms of complexity and in terms of power. FPGA-based runtime acceleration for DVB-T2 allows for unwrapping the iterative structures of modern channel decoding schemes by using parallel hardware designs. Additionally, due to the sequential nature of the DVB-T2 receiver chain we can use partial reconfiguration to switch between different decoding modules. We will show in a theoretical analysis that this time-multiplexing approach can be used to realize resource-efficient DVB-T2 receiver chains at a much lower resource and power consumption as compared to solely processor-based solutions. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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