| Autor: |
Haijun, Sun, Xuanming, Wang, Shaochong, Lei, Zhibiao, Shao |
| Zdroj: |
2012 International Conference on Image Analysis & Signal Processing; 1/ 1/2012, p1-5, 5p |
| Abstrakt: |
A novel allocated-by-weight seed-based BIST (ASB) architecture has been proposed for combinational circuits to test. A test sequence of ASB is termed as seeded weighted Gray cyclic shift sequence (SW-GCSS), generated by Gray cyclic shift sequence (GCSS) and canonical seeds. GCSS, termed as the characteristic sequence is a single input change (SIC) sequence with transitions of its bits different from each other. Based on theoretical deduction of the properties of canonical seeds, a novel algebraic model and an optimized algorithm have been developed, based on which a seed circuit is provided. SW-GCSS whose vectors are unique should be assigned to CUT (Circuit Under Test) according to weights to improve test efficiency. A method used to calculate and adjust weights is also given. Experimental results on the ISCAS85 benchmark circuits show that ASB architecture can achieve a 59.3%∼97.3% power reduction compared with LFSRs, while ensuring high fault coverage, less test patterns and low hardware overhead. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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