| Autor: |
Yang, Se-Hyun, Lee, Seogjun, Lee, Jae Young, Cho, Jeonglae, Lee, Hoi-Jin, Cho, Dongsik, Heo, Junghun, Cho, Sunghoon, Shin, Youngmin, Yun, Sunghee, Kim, Euiseok, Cho, Ukrae, Pyo, Edward, Park, Man Hyuk, Son, Jae Cheol, Kim, Chinhyun, Youn, Jeongnam, Chung, Youngki, Park, Sungho, Hwang, Seung Ho |
| Zdroj: |
2012 IEEE International Solid-State Circuits Conference; 1/ 1/2012, p214-216, 3p |
| Abstrakt: |
Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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