| Abstrakt: |
This paper describes the 22nm Intel® processor codenamed Ivy Bridge that integrates up to four high-performance Intel Architecture (IA) cores, a power/performance optimized graphics/media processing unit (GPU), as well as memory, PCIe, and display controllers in the same die. The Ivy Bridge architecture is derived from the second-generation Intel Core™ processor [2], seen in Fig. 3.1.1. The processor has about 1.4 billion transistors in about 160mm2 in its largest incarnation. It introduces several enhancements in power, performance, and features over its predecessor. The IA core adds a pipelined divider, a next page prefetcher, additions to the ISA for 16b floating point conversion, fast string moves, and fast access of the FS/GS base registers. The Graphics/Media block provides significantly improved performance along with DX11 API support. Further, display capabilities have been augmented with a third independent display pipeline. The on-die power management control unit (PCU) and its associated firmware have added several power and thermal optimizations to improve performance and yield within the existing platform power envelopes, as well as to improve idle power relative to its predecessor. Power gates are distributed throughout the cores, enabling the PCU to independently either reduce voltage to a state retention voltage, or turn off voltage to a given core, depending on the current core usage conditions. The processor also implements power gating for portions of the DDR I/O buffers, reducing CPU power consumption when memory is in “self-refresh” mode. To optimize core sleep time, Ivy Bridge incorporates smart interrupt routing logic, which sends interrupts to active cores. The PCU also analyzes the processor's inherent voltage-frequency dependency to determine the optimum operating voltages across the entire dynamic range of operation (Fig. 3.1.2). The processor uses die temperature to estimate power and energy consumption in order to maximize performance. [ABSTRACT FROM PUBLISHER] |
