| Autor: |
Otsuga, Kazuo, Onouchi, Masafumi, Igarashi, Yasuto, Ikeya, Toyohito, Morita, Sadayuki, Ishibashi, Koichiro, Yanagisawa, Kazumasa |
| Zdroj: |
2012 IEEE International SOC Conference; 1/ 1/2012, p11-14, 4p |
| Abstrakt: |
We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm2. To suppress the AC voltage drop due to large load transient (LLT), we developed a LLT control method using dynamic sampling clock frequency scaling scheme. The measurement results show that the AC voltage drop can be suppressed to 50%. The peak efficiency is 99% at 250 mA. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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