| Autor: |
Jayaraman, Balaji, Gupta, Sneha, Zhang, Yanli, Goyal, Puneet, Ho, Herbert, Krishnan, Rishikesh, Fang, Sunfei, Lee, Sungjae, Daley, Douglas, McStay, Kevin, Wunder, Bernhard, Barth, John, Deshpande, Sadanand, Parries, Paul, Malik, Rajeev, Agnello, Paul, Stiffler, Scott, Iyer, Subramanian S. |
| Zdroj: |
2012 IEEE International Conference on IC Design & Technology; 1/ 1/2012, p1-4, 4p |
| Abstrakt: |
In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap) offer significant area advantage over the other two conventional decoupling capacitors - Metal-oxide-semiconductor (MOS) and Metal-Insulator-Metal (MIM). The fabrication process flow of DT decap is borrowed from regular eDRAM process and adds no additional process cost to processors that utilize large eDRAM cache [1]. We demonstrate that, with new process innovations such as introduction of High-k/metal gate and new plate doping methodology, there is significant reduction in equivalent series resistance (ESR) of the trench resulting in ∼3.5X improvement in half capacitance frequency for 32nm node. Further, with 22nm technology, improved ESR, DT Decaps performance is significantly enhanced, hence showing that DT-decaps can be reliably used for technology beyond 32nm. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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