| Autor: |
Uemori, Satoshi, Ishii, Masamichi, Kobayashi, Haruo, Doi, Yuta, Kobayashi, Osamu, Matsuura, Tatsuji, Niitsu, Kiichi, Arakawa, Yuta, Hirabayashi, Daiki, Yano, Yuji, Gake, Tatsuhiro, Takai, Nobukazu, Yamaguchi, Takahiro J. |
| Zdroj: |
2012 IEEE Asia Pacific Conference on Circuits & Systems; 1/ 1/2012, p671-674, 4p |
| Abstrakt: |
This paper describes the architecture and principles of operation of sigma-delta (ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe a multi-bit ΣΔ TDC architecture for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose a self-calibration method that measures delay values using an improved ring oscillator circuit to improve the overall TDC linearity. Our MATLAB simulation results demonstrate the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
