| Autor: |
Chang, Yuan-Teng, Chung, Wen-Hao |
| Zdroj: |
2012 IEEE 55th International Midwest Symposium on Circuits & Systems (MWSCAS); 1/ 1/2012, p984-987, 4p |
| Abstrakt: |
This paper presents a fast fractional motion estimation (FME) and the associated VLSI architecture for H.264/AVC multiview video coding. The proposed FME automatically turns off the mode P8×8 by exploiting the results of integer motion estimation and similarity between views. In addition, the fraction-pel refinement of integer motion or disparity vector in any partition may be skipped according to the difference of their rate-distortion cost. This algorithm accelerates the FME by nearly 50% with negligible PSNR degradation and bitrate increase. The resultant FME can process a macroblock within 612 clock cycles, enough to achieve real-time coding for the stereoscopic HD1080p video sequences operating at frequency of 300 MHz. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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