| Autor: |
Rajaraman, V., Koning, J. J., Ooms, E., Pandraud, G., Makinwa, K. A. A., Boezen, H. |
| Zdroj: |
2012 IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS); 1/ 1/2012, p220-223, 4p |
| Abstrakt: |
This paper describes a new post-CMOS technology for co-integrating thick (> 50 μm) high aspect ratio MEMS beneath a thin-SOI (1.5 μm) CMOS platform, in the low resistivity SOI-handle wafer. MEMS postprocessing requires just one photomask step. The low resistance (∼ 40 Ω) electrical interconnection between CMOS and MEMS is realized using vertically embedded polysilicon interconnects, formed during standard CMOS processing. Electrical isolation achieved using isolation trenches shows a small leakage current (< 10−12 A) and a typical isolation resistance better than 1012 Ω. Measurements indicate that backside micromachining adjacently-beneath integrated transistors does not affect their characteristics. This 3D integration technology can be applied for fabricating a variety of MEMS devices like capacitive inertial sensors and electrostatic actuators requiring thick, high aspect ratio microstructures with high density electrical interconnection. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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